1. Field of the Invention
The present invention relates generally to serial bus communication, and more particularly to enabling multi-master operation of serial bus devices in a blade server environment.
2. Background of the Related Art
In a computer system, a bus provides a communication pathway between hardware devices. A parallel bus is one category of computer system bus having multiple address and data signal lines for communicating multiple bits in parallel. The width of a parallel bus relates to the number of parallel lines in the bus and a corresponding number of bits that may be simultaneously communicated on the parallel bus. The rate of data transfer on a parallel bus for a given clock frequency is dependent on the bus width. Parallel buses are commonly used with certain, so-called “high speed” peripheral or memory devices. An example of a parallel bus is the Peripheral Component Interconnect (PCI) bus.
A serial bus, by contrast, sends data bits sequentially, i.e. one bit at a time. Serial communication typically involves differential signaling, wherein the magnitude of a dynamic voltage differential between a pair of conductors at a given clock cycle determines the bit value. A serial bus may be used, for example, to enable a system processor to communicate with an analog to digital converter which measures battery voltage. Despite the limitation of sequential bit transmission, a serial bus may operate at a high clock speed, which allows for very high data rates. A computer system may include one or more parallel bus and one or more serial bus, wherein each bus may be used for communication between a different subsystem of components.
Various bus standards have been created. Devices designed according to the same bus standard may communicate with one another using that bus standard. One well known serial bus standard is the Inter-Integrated Circuit bus (abbreviated “I2C”). I2C allows attached low-speed peripherals to communicate with a controller. Examples of low-speed hardware in a blade server environment that may operate on an I2C bus include temperature sensors, light-emitting diodes (LEDs), vital product data (VPD) storage devices, and general purpose input/output (GPIOs) pins on an integrated circuit. Any or all of these devices may be connected to a Service Processor or Management Controller (MC) to enable communication between the devices and the Service Processor or MC.
Bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate transactions over the bus. The controlling device is referred to as a “master device,” and the controlled device is referred to as a “slave device.” When controlling a slave device, the master device is said to “master” the bus. Slave devices are more passive than master devices. For example, a slave device may only communicate in response to a communication initiated by a master device. Only one device at a time can control communication over the bus. A slave may be a receive-only device, or it may respond to an inquiry from a master device. In either case, a master device provides and drives the clock signal used to synchronize the data line. The I2C bus comprises a serial clock line and a serial data line. To initiate a communication with a slave device on an I2C bus, a master drives the clock line and synchronously sends out a multi-bit address on the data line. Each slave device on the I2C bus is responsive to a specific address. When a slave detects its specific address, the slave device initiates a function.
Most modern bus architectures, including I2C, allow multiple devices to master a bus, in a process known as multi-mastering. The I2C protocol, for example, includes a multi-master suite of optional protocols and chips that allow a slave to be mastered by more than one MC. In a multi-master operation, the I2C standard includes an arbitration process to determine which master will gain control of the bus. Each device needs to be able to cooperate with the fact that another device is currently talking and the bus is therefore busy. Following the usual arbitration logic, if two devices start to communicate at the same time, the one writing more zeros to the bus (or the slower device) wins the arbitration and the other device immediately discontinues any operation on the bus. Also, each device must detect an ongoing bus communication and must not interrupt it. This is conventionally achieved by recognizing traffic and waiting for a stop condition to appear before starting to talk on the bus.
However, due to various design considerations, such as design and manufacturing costs, not all devices capable of mastering an I2C bus are designed to support the multi-master feature of I2C. In a blade server system, for example, the management controller (MC) and various I2C chips are commonly designed without multi-master capabilities. If a single-master and a multi-master device are both connected to an I2C bus, the single-master may attempt to communicate over the bus while the multi-master is already communicating over the bus. This simultaneous use of the bus can cause unpredictable results, such as data corruption. The same type of problem can occur between two single-master devices coupled to the same bus.